This relates to integrated circuits and more particularly, to systems for designing logic circuitry on integrated circuit devices such as programmable integrated circuits.
Programmable integrated circuits are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design tools to design a custom logic circuit that performs custom logic functions. When the design process is complete, the computer-aided design tools generate configuration data. The configuration data is loaded into memory elements to configure the devices to perform the functions of the custom logic circuit. Memory elements are often formed using random-access-memory (RAM) cells. Because the RAM cells are loaded with configuration data during device programming, the RAM cells are sometimes referred to as configuration memory or configuration random-access-memory cells (CRAM).
Integrated circuits such as programmable integrated circuits often include millions of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto an integrated circuit (target device). Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are high-level compilation and hardware description language (HDL) compilation. High-level compilation (or “high-level synthesis”) involves generating an HDL file of a system from a computer language description of the system. The computer language description of the system may be, for example, in Open Computing Language (OpenCL) format or another computer language description format. OpenCL is a framework for writing programs that execute across heterogeneous platforms. OpenCL includes a language for writing kernels and application programming interfaces (APIs) that are used to define and control platforms. HDL compilation involves performing synthesis, placement, routing, and timing analysis of the system on the target device and providing final configuration data for the target device to implement the desired system.
Traditionally, synthesis is performed independently of information from other compilations. As a result, the HDL compiler must compile the HDL file without any knowledge of whether the final configuration data performs efficiently or satisfactorily when loaded onto the target device. As a result, the target device may have unoptimized and inefficient performance when loaded with the configuration data.